International Workshop on
High Performance Dynamic Reconfigurable Systems and Networks
CALL FOR PAPERS AND PARTICIPATION
As part ofThe International Conference on High Performance Computing & Simulation (HPCS 2016)
July 18 – July 22, 2016
Paper Submission Deadline: April 14, 2016 - Extended
Submissions could be for full papers, short papers, poster papers, or posters
SCOPE AND OBJECTIVES
Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs - as opposed to conventional bus-based communication architectures - is already established in a variety of architectures.
While there is considerable maturity in the area of NoC and RS architectures, there is that familiar gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.
More specifically, the challenges -- and the corresponding opportunity for innovation -- can be broken down into four broad categories: programming, compilers, run-time infrastructures, and the architectures themselves. Wider adoption, especially of reconfigurable systems, is contingent on a synergetic development and maturity across these areas. Lack of such a synergy has been a major hurdle to RS and specifically FPGAs becoming more mainstream, but there are very strong indicators in the academia and the industry that this is changing. High Performance Reconfigurable Computing (HPRC) is specially getting widespread interest.
DRSN 2016 workshop is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and NoCs in high-performance and/or power-efficient systems. The challenges to wider adoption of these technologies, arising out of programming environments, compilers, and runtime systems are of special interest to this workshop, along with innovations at the architectural level.
The DRNS Workshop topics of interest include (but are not limited to) the following:
Compilation, Programming Languages, and Domain-Specific Languages for HPRC
Tools, Frameworks, Design-flows for developing high-performance reconfigurable systems
Virtual Machines, Middleware, Run-time and Operating Systems
Applications of FPGAs and RS, including big-data and big-compute applications
Heterogeneous high performance computing
High-level and pure software programming for reconfigurable computing architectures
Tools for design space exploration of reconfigurable systems and NoC-based systems
Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with reconfigurable architectures using FPGAs
Novel NoC Architectures for high-performance systems
Systems software support for advanced NoC-based systems
NoC-aware compilation and runtime systems
Reliability, scalability, availability, and fault tolerance
Area, energy, and performance evaluation
Case studies and FPGA-based implementation of reconfigurable systems and NoC-based systems
Mapping and scheduling of tasks onto NoC-based systems
Self-reconfiguration and self-optimization for HPC
Reconfigurable computing education
INSTRUCTIONS FOR AUTHORS:
You are invited to submit original and unpublished research works on above and other topics related to dynamic reconfigurable systems and networks. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2016.cisedu.info/1-call-for-papers/call-for-posters for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript to the workshop paper submission EasyChair site at https://easychair.org/conferences/?conf=drsn2016. Acknowledgement will be sent within 48 hours of submission.
Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2016 conference to present the paper at the workshop.
Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2016 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in all major indexing services accordingly.
A planned special issue of the Journal Concurrency and Computation: Practice and Experience will be available for selected papers of the conference. Best papers will be invited to submit an extended version.
If you have any questions about paper submission or the workshop, please contact the track organizers.
Paper Submissions: --------------------------------------- April 14, 2016 - Extended
Acceptance Notification: --------------------------------- April 28, 2016
Camera Ready Papers and Registration Due by: ------ May 21, 2016 - Extended
Conference Dates: --------------------------------------- July 18 – 22, 2016
School of Computing Science, University of Glasgow
18 Lilybank Gardens, S122, Glasgow G12 8QQ, U.K.
Phone: +44 141 330 1632
Syed Waqar Nabi
School of Computing Science, University of Glasgow
Sir Alwyn Williams Building, 405, Glasgow G12 8QQ, U.K.
Phone: +44 141 330 2074
International Program Committee*:
All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2016 and will be published as part of the HPCS 2016 Proceedings.
Hideharu Amano, Keio University, Japan
Sairahul Chalamalasetti, Hewlett Packard, USA
Rene Cumplido, National Institute for Astrophysics, Optics, and Electronics - INAOE, Mexico
Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden
Martin Herbordt, Boston University, Massachusetts, USA
Miriam Leeser, Northeastern University, Massachusetts, USA
Martin Margala, University of Massachusetts - Lowell, Massachusetts, USA
Nasibeh Nasiri, University of Massachusetts-Lowell, Massachusetts, USA
Jari Nurmi, Tampere University of Technology, Finland
Muhammad Adeel Pasha, Lahore University of Management Sciences (LUMS), Pakistan
Thilo Pionteck, University of Lübeck, Germany
Oren Segal, University of Massachusetts-Lowell, Massachusetts, USA
Aaron Smith, Microsoft Research Redmont, Washington, USA
Dirk Stroobandt, Ghent University, Belgium
Zain Ul-Abdin, Halmstad University, Sweden
For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs2016.cisedu.info/ or http://cisedu.us/rp/hpcs16 or contact one of the Conference's organizers.