Workshop06-APMM

The 6th International Workshop on New Algorithms and Programming Models

for the Manycore Era

(APMM 2016)

CALL FOR PAPERS AND PARTICIPATION

As part of

The International Conference on High Performance Computing & Simulation (HPCS 2016)

http://hpcs2016.cisedu.info or http://cisedu.us/rp/hpcs16

July 18 – July 22, 2016

Innsbruck, Austria

Submission Deadline: April 14, 2016 - Extended

Submissions could be for full papers, short papers, poster papers, or posters

SCOPE AND OBJECTIVES

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance. In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, Intel SCC, integrated GPUs etc.) add further challenges to efficient programming in HPC applications.

Therefore, compute and data intensive tasks can only benefit from the hardware's full potential, if both processor and architecture features are taken into account at all stages - from the early algorithmic design, via appropriate programming models, up to the final implementation.

The APMM Workshop topics of interest include (but are not limited to) the following:

• Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).

• Manycore-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.

• Parallelisation on HPC platforms; esp. platforms with hierarchical communication layout, multi-/many-core platforms, NUMA architectures, or accelerator components (Intel Xeon Phi, NVIDIA and AMD GPU, Tilera, FPGA, integrated GPUs (such as AMD APUs or Intel Haswell/Ivy Bridge)).

• Parallelisation with appropriate programming models and tool support for multi-core and hybrid platforms.

• concepts for exploiting emerging vector extensions of instruction sets

• Software engineering, code optimisation, and code generation strategies for parallel systems with multi-core processors.

• Tools for performance and cache behavior analysis (including cache simulation) for parallel systems with multi-core processors.

• Performance modelling and performance engineering approaches for multi-thread and mutli-process applications.

INSTRUCTIONS FOR PAPER SUBMISSIONS:

You are invited to submit original and unpublished research works on above and other topics related to Many-core computing. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2016.cisedu.info/1-call-for-papers/call-for-posters for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.

Submit a PDF copy of your full manuscript to the workshop paper submission EasyChair site at xxx. Acknowledgement will be sent within 48 hours of submission.

Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2016 conference to present the paper at the workshop.

Proceedings

Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2016 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in all major indexing services accordingly.

A planned special issue of the Journal Concurrency and Computation: Practice and Experience will be available for selected papers of the conference. Best papers will be invited to submit an extended version.

If you have any questions about paper submission or the workshop, please contact the track organizers.

IMPORTANT DATES

Paper Submissions: --------------------------------------- April 14, 2016 - Extended

Acceptance Notification: --------------------------------- April 28, 2016

Camera Ready Papers and Registration Due by: ------ May 21, 2016 - Extended

Conference Dates: --------------------------------------- July 18 – 22, 2016

International Program Committee:

All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2016 and will be published as part of the HPCS 2016 Proceedings.

• TBA, TBA