Workshop17-AASC

International Workshop on Architecture-Aware Simulation and Computing
(AASC 2016)


CALL FOR PAPERS


As part of
The International Conference on High Performance Computing & Simulation (HPCS 2016)

July 18 – July 22, 2016
Innsbruck, Austria 


Submission Deadline: April 21, 2016 - Extended

Submissions could be for full papers, short papers, poster papers, or posters


BACKGROUND AND OBJECTIVES
To keep pace with the performance increase predicted by Moore's Law, homogeneous/heterogeneous processor aggregates have been extensively adopted both at the High Performance Computing (HPC) and at the embedded system domains. However, such steadily increase (often attained by simply scaling the number of computing cores within a chip) has been threatened by several architectural and technological constraints: limited parallelization opportunities (either at data, task, or even at instruction level); reduced memory throughput and complex cache hierarchies; limited communication bandwidth; thermal, power and energy constraints, etc. 

On the other hand, the prevailing heterogeneous computing architectures, often integrating different types of coprocessors (e.g., Intel Xeon Phi) and accelerator components (e.g., GPUs, FPGAs, etc.) has introduced complex challenges to efficiently program and implement HPC applications. 

On the embedded domain, different compromises to cope with strict energy efficiency requirements have been demanded. Despite the several different approaches that have been considered either at the processor architecture level (e.g., ARM big.LITTLE clusters) or at the coprocessor/accelerator level (e.g., mobile GPUs, reconfigurable SoCs, etc.), complex challenges are still posed in order to attain the ever increasing performance levels that have also been claimed in this specific domain. 

Therefore, it is widely recognized that next generation HPC and embedded systems can only benefit from the hardware’s full potential if both processor and architecture features are taken into account at all development stages - from the early algorithmic design to the final implementation stage. 

The AASC workshop strives to address all aspects related to these issues, including, but not limited to:

  • Hardware-aware compute/memory-intensive simulations of real-world problems in computational science and engineering domains (e.g., applications in electrical, mechanical, physics, geological, biological, or medical engineering).
  • Architecture-aware approaches for large-scale parallel computing, including scheduling, load-balancing and scalability studies.
  • Architecture-aware parallelization on HPC platforms, including multi-/many-core architectures comprising coprocessor/accelerator components (e.g., Intel Xeon Phi, GPUs, FPGAs, etc.).
  • Architecture-aware approaches for energy-efficient implementations of HPC or embedded applications (e.g., ARM big.LITTLE, mobile GPUs, reconfigurable SoCs, etc.).
  • Programming models and tool support for parallel heterogeneous platforms (e.g., CUDA, OpenCL, OpenACC, etc.).
  • Software engineering, code optimization, and code generation strategies for parallel systems with multi-/many-core processors.
  • Performance and memory optimization tools and techniques (including cache optimization, data reuse, data streaming, etc.) for parallel systems with multi-core processors.

INSTRUCTIONS FOR PAPER SUBMISSIONS
:
You are invited to submit original and unpublished research works on above and other topics related to Architecture-Aware Simulation and Computing.  Submitted papers must not have been published or simultaneously submitted elsewhere.  
For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to  http://hpcs2016.cisedu.info/1-call-for-papers/call-for-posters for posters submission details) will also be considered. Please specify the type of submission you have.  Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. 

Submit a PDF copy of your full manuscript to the Workshop paper submission EasyChair site at https://easychair.org/conferences/?conf=aasc2016.  Acknowledgement will be sent within 48 hours of submission. 

Only PDF files will be accepted, uploaded to the submission link above.  Each paper will receive a minimum of three reviews.  Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references.  Submission implies the willingness of at least one of the authors to register and present the paper, if accepted.  At least one of the authors of each accepted paper will have to register and attend the HPCS 2016 conference to present the paper at the Workshop. 

PROCEEDINGS
Accepted papers will be published in the conference proceedings which will be made available at the time of the meeting. Instructions for final manuscript format and requirements will be posted on the HPCS 2016 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in major indexing services accordingly. 

If you have any questions about paper submission or the workshop, please contact the workshop organizers. 


IMPORTANT DATES
Paper Submissions: ------------------------------------------ April 21, 2016 - Extended
Acceptance Notification: ------------------------------------  April 28, 2016
Camera Ready Papers and Registration Due by: ---------  May 21, 2016 - Extended
Conference Dates:  ------------------------------------------- July 18 – 22, 2016


WORKSHOP ORGANIZERS

David Parello
    Laboratoire LIRMM, Université de Perpignan, Perpignan, France
    Phone: +33 (0)4 68 66 21 25  
    Fax:     +33 (0)4 68 66 22 87
    Email:   
David.Parello@univ-perp.fr 

George Karypis
    
Department of Computer Science & Engineering
    University of Minnesota - Twin Cities, Minnesota, USA  
    Phone: +1 (612) 626-7524 
    Fax:     +1 (612) 625-0572 
    Email:   karypis@cs.umn.edu


International Program Committee*:  
All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2016 and will be published as part of the HPCS 2016 Proceedings. 
  • Ramon Canal, UPC, Spain
  • Sylvain Collange, INRIA/IRISA, France
  • David Defour, DALI-LIRMM Université de Perpignan, France
  • Christophe Dubach, University of Edinburgh, U.K.
  • Sylvain Girbal, Thales Research and Technology (TRT), France
  • Bernard Goossens, Université de Perpignan Via Domitia, France
  • Yves Lhuillier, CEA - Commissariat à l'énergie atomique et aux énergies alternatives, France
  • Daniel Gracia Pérez, Thales Research & Technology, France
  • Sebastian Pop, Samsung Austin R&D Center, USA
  • Louis-Noel Pouchet, Ohio State University, Ohio, USA
  • Sami Yehia, Intel Corporation, Oregon, USA


For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs2016.cisedu.info/ or http://cisedu.us/rp/hpcs16  or contact one of the Conference's organizers. 


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